In Saarland, Germany, Wolfspeed intends to construct a state-of-the-art, highly automated 200 mm wafer fabrication facility. Creating a ground-breaking innovation in SiC device development and production in the European Union to support growing demand for a wide range of automotive, industrial, and energy applications, the company's first fab in Europe will be its most advanced.
The European Commission must approve state aid before the Wolfspeed facility can be built as part of a collaboration under the IPCEI for Microelectronics and Communication Technologies. Technology development and initial deployment within this project are intended to be supported by IPCEI funding. ZF Friedrichshafen also plans to contribute financially to the new construction as part of a new strategic alliance that was separately announced.
The company's $6.5 billion capacity expansion initiative, which includes the opening of its 200 mm Mohawk Valley device fab in April 2022 and the building of The John Palmour Manufacturing Center for Silicon Carbide, a 445-acre (180 hectare) Silicon Carbide materials facility in North Carolina, which will increase the company's current materials capacity by more than 10x, includes the announcement of the European fab. By the end of FY2024, the first stage of building the materials facility should be finished.
The announcement was made at a gathering on the 35-acre (14-hectare) site of the proposed fab, a former coal-fired power plant in Saarland, Germany. A joint Silicon Carbide RandD facility in Germany that is a part of the same IPCEI framework, as well as an investment in Wolfspeed, were also part of the strategic alliance between Wolfspeed and ZF that was also announced. Subject to EU Commission approval, it is anticipated that fab construction will start in the first half of 2023.
In order to produce the next generation of SiC devices, the fab will be built for ground-breaking manufacturing techniques. A model for more sustainable fabs in the future, the new fab will also use cutting-edge sustainability practices, such as high percentages of recycled water and a smaller carbon footprint. When fully operational, the fab will have more than 600 workers.
The use of SiC devices is spreading quickly across many industries, including traction and variable speed drives, industrial power supplies, renewable energy and energy storage, electric vehicles, charging infrastructure, and electric vehicles. Numerous new clean energy applications are made possible by silicon carbide, which enables smaller, lighter, and more affordable designs.
Surge energy robustness is a requirement for power devices used in demanding applications such as electrical grids and automotive powertrains. GaN HEMTs lack the ability to use avalanche to dissipate surge energy, whereas Si and SiC MOSFETs can. In the unclamped inductive switching (UIS) test, this article investigates the cascode GaN HEMT's repetitive surge energy robustness at 650 V. A crucial component of the overall GaN HEMT reliability is surge capability and the safe operating range under this stress.
According to recent studies, the enhancement-mode (E-mode) p-gate GaN HEMT can withstand the surge energy via resonant energy transfer between the device output capacitance and load inductor. During this transfer, the drain-to-source voltage (VDS) of the GaN HEMT displays a resonant waveform. The device fails at the transient when the peak resonant voltage reaches the dynamic breakdown voltage (BV), which may differ significantly from the static BV [2], [3].
A depletion-mode (D-Mode) high-voltage GaN HEMT and an E-mode low-voltage Si MOSFET combine to form cascode GaN HEMTs, which operate as a single E-mode high-voltage device (Figure 1a). It is found that under repeated surge energy stresses compared to a single stress, the failure boundary of the cascode GaN HEMT reliability is smaller. Continual surge energy stresses on the device also cause significant degradations.
UIS test for a single event.
The DUT is a TO-247-packaged, commercial 650-V, 50-m cascode GaN HEMT (Figure 1b) [4]. A vertical Si MOSFET is stacked onto the GaN HEMT, and its drain pad is electrically connected to the source pad of the GaN HEMT. Si MOSFET's avalanche breakdown voltage (BVAVA) is 35 V, while the threshold voltage of HEMTs is -22 V.
Figure 1c displays the UIS test circuit schematic. There are two parts to the UIS test. In the first, the DUT is turned ON, and the load inductor is charged by VDD; in the second, the DUT is turned OFF, and the energy stored in the inductor is made to pass through the DUT. The UIS evaluation system is depicted in Figure 1d, and it consists of a motherboard (with the main power loop and bus capacitors) and a daughterboard (with the DUTs and three test points).
Two failure modes of GaN cascode HEMTs were observed while researching the GaN HEMT reliability under the single-event UIS stress: a short between the HEMT drain and gate and a short between the HEMT drain and source. The failure modes and failure voltages of 30 DUTs measured at 25°C and 150°C under three different sizes of load inductors are shown in Figures 2(a) and (b), respectively. The outcomes of the BV measurement of 6 DUTs on a curve tracer are instead displayed in Figure 2(c). These findings suggest that under the single-event UIS stress, the second failure mode is more reliable.
recurring UIS test.
For these multiple UIS tests, the pulse period is fixed at 10 seconds. The peak VDS is modulated by the inductor charging time during each UIS pulse, which is typically 3 s and constant throughout a specific repeating UIS test. Figure 4a displays the DUT waveforms under a single UIS stress with a peak voltage of 1 point 25 kV; Figure 4b displays the waveforms under repeated UIS stresses with the same peak voltage; and Figure 4c displays the zoomed-in waveform of the DUT during the single-event UIS test. The comparison of the DUT's UIS waveforms at the beginning and end of the 1-million-cycle repetitive UIS stresses is shown in Figure 4d, and the waveform of the DUT's failure during the UIS test is shown in Figure 4e, validating the failure at the peak transient VDS, i.e. e. , the same UIS failure behaviors when compared to p-gate GaN HEMT
To investigate the failure and degradation of cascode GaN HEMTs under repeated UIS stresses, a total of 20 DUTs were put through a million cycles of testing. The safe operating area of the GaN HEMT can then be defined and understood under repeated UIS tests.
No DUTs reached a million cycle threshold when the peak VDS was greater than 1.35 kV (Figure 5). It was discovered that the DUTs could withstand 10,000 cycles at 1 point 4 kV peak VDS and 100,000 cycles at 1 point 35 kV peak VDS. Under repeated UIS stresses, the cascode GaN HEMT's true failure boundary is lower (by about 1 point 3 kV) than it is under a single UIS stress and below the static BV.
In order to investigate the relationship between DUT degradation and the magnitude of the peak UIS voltage and temperature, a total of 4 DUTs were tested under 1-million-cycle UIS stresses with a peak voltage of 1.25 kV and 1.3 kV at both 25°C and 150°C.
The degradation and recovery behaviors of the 4 DUTs are remarkably similar (Figure 6). There is almost no statistically significant correlation between the DUT degradation/recovery behaviors and the peak UIS VDS or the temperature, according to additional DUTs that have been tested under the same conditions.
Explanation of Surge Behavior for GaN HEMT Reliability.
Under repeated UIS stresses, the degradation and recovery characteristics of the DUTs can be explained by the buffer trapping accumulation in the GaN HEMT. During each UIS stress, electrons from the source or the interface between transition layers and the p-type Si substrate can more easily be injected into the GaN buffer region due to high VDS. Under repeated UIS stressors, it is anticipated that the buffer trapping will build up and possibly even saturate.
The trapped electrons in the buffer will drain the two-dimensional electron gas, increasing the RDS (ON). As a result of the trapped electrons raising the potential barrier in the depletion region, the IDSS will decrease in the interim. Finally, buffer trapping will enlarge the depletion region, which will help to clarify why CDS decreased after the UIS stressors. The observed slow recovery of the parametric shifts is explained by the trapped electrons in the buffer zone, which gradually detrap as the recovery period lengthens.
The lower dynamic BV due to the stronger buffer trapping can be used to explain why the failure boundary (peak VDS) in the repetitive UIS tests is lower than the one in the single-event UIS test.
Using microscopic images of the decapsulated DUTs, Silvaco Atlas has been used to simulate TCAD devices, with the simulated devices' structures being determined by the images. The model shows however notable parametric shifts, including RDS(ON) increase, IDSS decrease, and CDS decrease, confirming that DUT is capable of withstanding 1 million UIS cycles when the peak voltage is below 1.3 kV. After an hour, these parametric shifts can be largely recovered. The accumulation of buffer trapping in GaN HEMTs and the resulting changes in dynamic BV can be used to explain the aforementioned device failure and degradation behaviors. These findings enhance our comprehension of the robustness of cascode GaN HEMTs and offer important references for the converter design margins.
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